Intel Specific Instructions

SlashLP97

New member
May 3, 2020
4
0
1
Hey everyone! Thanks to all of the brilliant people at amd-osx an these forums I have my 3700x system up and running extremely well! The only issue I have is that there are some programs that seem to compile with Intel specific instructions (the most common seems to be _intel_fast_memset). I know this is an app specific thing and not a kernel issue, but is it planned to have a workaround for this anytime in the future? It would be awesome if there was a .dylib analyzer or something that was able to go in and change the machine code to use regular memset if it found the Intel specific one(s).

Thanks!
 

SlashLP97

New member
May 3, 2020
4
0
1
Edit for additional question: Would there be a way to develop a patch for certain applications in the same way that there are patches for Adobe products? If so, who would I need to pay to help me? haha

Very cool, thanks for the info! I'm guessing there would be a pretty heft performance hit if every opcode were inspected fro compatibility though, right?
 
Last edited:

turbo

New member
Jul 29, 2020
3
0
1
is there a list of the opcodes that are missing or different in recent AMD CPUs (say r3600 or newer) ? I don't have an AMD CPU yet, but I have a bunch of experience building opcode emulators. The opemu project goes all the way back to SSE3 which I have to imagine AMD CPUs have implemented by now.

A crash dump from that specific app would probably be telling.
 

Shaneee

Administrator
Staff member
Mar 13, 2020
285
107
142
28
Scotland
amd-osx.com
@turbo Yes AMD has SSE3 now. These are the features listed on my 3600 in macOS,

Code:
machdep.cpu.features: FPU VME DE PSE TSC MSR PAE MCE CX8 APIC SEP MTRR PGE MCA CMOV PAT PSE36 CLFSH MMX FXSR SSE SSE2 HTT SSE3 PCLMULQDQ MON SSSE3 FMA CX16 SSE4.1 SSE4.2 MOVBE POPCNT AES XSAVE OSXSAVE AVX1.0 RDRAND F16C

machdep.cpu.leaf7_features: RDWRFSGS BMI1 AVX2 SMEP BMI2 PQM PQE RDSEED ADX SMAP CLFSOPT CLWB SHA UMIP RDPID

machdep.cpu.extfeatures: SYSCALL XD 1GBPAGE EM64T LAHF LZCNT PREFETCHW RDTSCP TSCI
 

turbo

New member
Jul 29, 2020
3
0
1
thanks, that's a good start! I'm guessing for the _intel_fast_memset/memcpy that the app is deciding to take this path based on something advertised in the features that shouldn't be there. It should be easy to fail that check (could be AVX1.0?) and force the "slow" path (or patch the dylib to jmp to _memset)
 

Shaneee

Administrator
Staff member
Mar 13, 2020
285
107
142
28
Scotland
amd-osx.com
If it's feature based my guess would be EM64T but considering all Mac devices use Intel CPUs (for now) it's just the default.
 

turbo

New member
Jul 29, 2020
3
0
1
I suspect it's a more specific check than that, somebody else has done most of the research already

could you run a "sysctl hw.optional" and post the output of that from the 3600?
 

Shaneee

Administrator
Staff member
Mar 13, 2020
285
107
142
28
Scotland
amd-osx.com
Sure here it is,

Code:
[email protected] ~ % sysctl hw.optional
hw.optional.floatingpoint: 1
hw.optional.mmx: 1
hw.optional.sse: 1
hw.optional.sse2: 1
hw.optional.sse3: 1
hw.optional.supplementalsse3: 1
hw.optional.sse4_1: 1
hw.optional.sse4_2: 1
hw.optional.x86_64: 1
hw.optional.aes: 1
hw.optional.avx1_0: 1
hw.optional.rdrand: 1
hw.optional.f16c: 1
hw.optional.enfstrg: 0
hw.optional.fma: 1
hw.optional.avx2_0: 1
hw.optional.bmi1: 1
hw.optional.bmi2: 1
hw.optional.rtm: 0
hw.optional.hle: 0
hw.optional.adx: 1
hw.optional.mpx: 0
hw.optional.sgx: 0
hw.optional.avx512f: 0
hw.optional.avx512cd: 0
hw.optional.avx512dq: 0
hw.optional.avx512bw: 0
hw.optional.avx512vl: 0
hw.optional.avx512ifma: 0
hw.optional.avx512vbmi: 0